\doxysection{SDMMC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_s_d_m_m_c___type_def}{}\label{struct_s_d_m_m_c___type_def}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}}


Secure digital input/output Interface.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_ab241f9bc57b5606c7cdad92a94130b5e}{POWER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_ac432d7f247e2f199f387a9d81a70dbe3}{CLKCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_aa4a8ca4a55a6c1b0d2837bb1490efea6}{ARG}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_ad67342999b4fb5e7c7249935ea96d02f}{CMD}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a33c78086429a7eed4d57a5633a9d78f2}{RESPCMD}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_aca71c167ec5fbe3884109e0bd3fb51fb}{RESP1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a3f1ab9eeca1d08e5fc50b6a8a0ee0257}{RESP2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_ae4a9250b0100c1a251354d64dde42300}{RESP3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_aebd8ffdd133537059f29fd5fecd6e290}{RESP4}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_abce8a3725f3ea302da79e28f75ed8e5f}{DTIMER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a4e2ca4e135c5074163d108bea39330fc}{DLEN}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_aa179173b3d0e158365b13f9ccdad1665}{DCTRL}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a8f6c92b986930f9f8a9f9ec3b557bb9a}{DCOUNT}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a9bbd3a78b1a7fb30c53e1d17a31b9b32}{STA}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a99775edb5f62c67e26fa0aa00293d51c}{ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a8f40e43afa9cf4ecf21c0cd1b2650560}{MASK}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a2b4dfe4d760d0522d58f64e409c0dd3b}{ACKTIME}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a98c802507f75fe3f2adfee84e38c409e}{RESERVED0}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a60742096500a81513c2331f206dcb8dc}{IDMACTRL}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_af0af1ac79c77322f6eed777232479dd9}{IDMABSIZE}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a18154fe330935603948726c1fb81ce8c}{IDMABASE0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a316749d0797c2d4525a3b5ba5a2dd205}{IDMABASE1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a499a7606959fd607830a7e2de16415cc}{RESERVED1}} \mbox{[}8\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_abf434e9dc8f9269c8bc0e703d0999f35}{FIFO}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a9c400d9cebb995b323b29a6aa0bce26d}{RESERVED2}} \mbox{[}222\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_s_d_m_m_c___type_def_a9a46a6f18da82b5ad11b8566b1cf0dfe}{IPVR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Secure digital input/output Interface. 

\label{doc-variable-members}
\Hypertarget{struct_s_d_m_m_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_s_d_m_m_c___type_def_a2b4dfe4d760d0522d58f64e409c0dd3b}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!ACKTIME@{ACKTIME}}
\index{ACKTIME@{ACKTIME}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ACKTIME}{ACKTIME}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a2b4dfe4d760d0522d58f64e409c0dd3b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+ACKTIME}

SDMMC Acknowledgement timer register, Address offset\+: 0x40 \Hypertarget{struct_s_d_m_m_c___type_def_aa4a8ca4a55a6c1b0d2837bb1490efea6}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!ARG@{ARG}}
\index{ARG@{ARG}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ARG}{ARG}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_aa4a8ca4a55a6c1b0d2837bb1490efea6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+ARG}

SDMMC argument register, Address offset\+: 0x08 \Hypertarget{struct_s_d_m_m_c___type_def_ac432d7f247e2f199f387a9d81a70dbe3}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!CLKCR@{CLKCR}}
\index{CLKCR@{CLKCR}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CLKCR}{CLKCR}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_ac432d7f247e2f199f387a9d81a70dbe3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+CLKCR}

SDMMC clock control register, Address offset\+: 0x04 \Hypertarget{struct_s_d_m_m_c___type_def_ad67342999b4fb5e7c7249935ea96d02f}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!CMD@{CMD}}
\index{CMD@{CMD}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CMD}{CMD}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_ad67342999b4fb5e7c7249935ea96d02f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+CMD}

SDMMC command register, Address offset\+: 0x0C \Hypertarget{struct_s_d_m_m_c___type_def_a8f6c92b986930f9f8a9f9ec3b557bb9a}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!DCOUNT@{DCOUNT}}
\index{DCOUNT@{DCOUNT}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DCOUNT}{DCOUNT}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a8f6c92b986930f9f8a9f9ec3b557bb9a} 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+DCOUNT}

SDMMC data counter register, Address offset\+: 0x30 \Hypertarget{struct_s_d_m_m_c___type_def_aa179173b3d0e158365b13f9ccdad1665}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!DCTRL@{DCTRL}}
\index{DCTRL@{DCTRL}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DCTRL}{DCTRL}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_aa179173b3d0e158365b13f9ccdad1665} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+DCTRL}

SDMMC data control register, Address offset\+: 0x2C \Hypertarget{struct_s_d_m_m_c___type_def_a4e2ca4e135c5074163d108bea39330fc}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!DLEN@{DLEN}}
\index{DLEN@{DLEN}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DLEN}{DLEN}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a4e2ca4e135c5074163d108bea39330fc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+DLEN}

SDMMC data length register, Address offset\+: 0x28 \Hypertarget{struct_s_d_m_m_c___type_def_abce8a3725f3ea302da79e28f75ed8e5f}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!DTIMER@{DTIMER}}
\index{DTIMER@{DTIMER}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DTIMER}{DTIMER}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_abce8a3725f3ea302da79e28f75ed8e5f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+DTIMER}

SDMMC data timer register, Address offset\+: 0x24 \Hypertarget{struct_s_d_m_m_c___type_def_abf434e9dc8f9269c8bc0e703d0999f35}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!FIFO@{FIFO}}
\index{FIFO@{FIFO}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FIFO}{FIFO}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_abf434e9dc8f9269c8bc0e703d0999f35} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+FIFO}

SDMMC data FIFO register, Address offset\+: 0x80 \Hypertarget{struct_s_d_m_m_c___type_def_a99775edb5f62c67e26fa0aa00293d51c}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a99775edb5f62c67e26fa0aa00293d51c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+ICR}

SDMMC interrupt clear register, Address offset\+: 0x38 \Hypertarget{struct_s_d_m_m_c___type_def_a18154fe330935603948726c1fb81ce8c}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!IDMABASE0@{IDMABASE0}}
\index{IDMABASE0@{IDMABASE0}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IDMABASE0}{IDMABASE0}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a18154fe330935603948726c1fb81ce8c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+IDMABASE0}

SDMMC DMA buffer 0 base address register, Address offset\+: 0x58 \Hypertarget{struct_s_d_m_m_c___type_def_a316749d0797c2d4525a3b5ba5a2dd205}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!IDMABASE1@{IDMABASE1}}
\index{IDMABASE1@{IDMABASE1}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IDMABASE1}{IDMABASE1}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a316749d0797c2d4525a3b5ba5a2dd205} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+IDMABASE1}

SDMMC DMA buffer 1 base address register, Address offset\+: 0x5C \Hypertarget{struct_s_d_m_m_c___type_def_af0af1ac79c77322f6eed777232479dd9}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!IDMABSIZE@{IDMABSIZE}}
\index{IDMABSIZE@{IDMABSIZE}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IDMABSIZE}{IDMABSIZE}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_af0af1ac79c77322f6eed777232479dd9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+IDMABSIZE}

SDMMC DMA buffer size register, Address offset\+: 0x54 \Hypertarget{struct_s_d_m_m_c___type_def_a60742096500a81513c2331f206dcb8dc}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!IDMACTRL@{IDMACTRL}}
\index{IDMACTRL@{IDMACTRL}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IDMACTRL}{IDMACTRL}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a60742096500a81513c2331f206dcb8dc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+IDMACTRL}

SDMMC DMA control register, Address offset\+: 0x50 \Hypertarget{struct_s_d_m_m_c___type_def_a9a46a6f18da82b5ad11b8566b1cf0dfe}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!IPVR@{IPVR}}
\index{IPVR@{IPVR}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IPVR}{IPVR}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a9a46a6f18da82b5ad11b8566b1cf0dfe} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+IPVR}

SDMMC data FIFO register, Address offset\+: 0x3\+FC \Hypertarget{struct_s_d_m_m_c___type_def_a8f40e43afa9cf4ecf21c0cd1b2650560}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!MASK@{MASK}}
\index{MASK@{MASK}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{MASK}{MASK}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a8f40e43afa9cf4ecf21c0cd1b2650560} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+MASK}

SDMMC mask register, Address offset\+: 0x3C \Hypertarget{struct_s_d_m_m_c___type_def_ab241f9bc57b5606c7cdad92a94130b5e}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!POWER@{POWER}}
\index{POWER@{POWER}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{POWER}{POWER}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_ab241f9bc57b5606c7cdad92a94130b5e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+POWER}

SDMMC power control register, Address offset\+: 0x00 \Hypertarget{struct_s_d_m_m_c___type_def_a98c802507f75fe3f2adfee84e38c409e}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a98c802507f75fe3f2adfee84e38c409e} 
uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+RESERVED0\mbox{[}3\mbox{]}}

Reserved, 0x44 -\/ 0x4C -\/ 0x4C \Hypertarget{struct_s_d_m_m_c___type_def_a499a7606959fd607830a7e2de16415cc}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a499a7606959fd607830a7e2de16415cc} 
uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+RESERVED1\mbox{[}8\mbox{]}}

Reserved, 0x60-\/0x7C \Hypertarget{struct_s_d_m_m_c___type_def_a9c400d9cebb995b323b29a6aa0bce26d}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a9c400d9cebb995b323b29a6aa0bce26d} 
uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+RESERVED2\mbox{[}222\mbox{]}}

Reserved, 0x84-\/0x3\+F8 \Hypertarget{struct_s_d_m_m_c___type_def_aca71c167ec5fbe3884109e0bd3fb51fb}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!RESP1@{RESP1}}
\index{RESP1@{RESP1}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESP1}{RESP1}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_aca71c167ec5fbe3884109e0bd3fb51fb} 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+RESP1}

SDMMC response 1 register, Address offset\+: 0x14 \Hypertarget{struct_s_d_m_m_c___type_def_a3f1ab9eeca1d08e5fc50b6a8a0ee0257}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!RESP2@{RESP2}}
\index{RESP2@{RESP2}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESP2}{RESP2}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a3f1ab9eeca1d08e5fc50b6a8a0ee0257} 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+RESP2}

SDMMC response 2 register, Address offset\+: 0x18 \Hypertarget{struct_s_d_m_m_c___type_def_ae4a9250b0100c1a251354d64dde42300}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!RESP3@{RESP3}}
\index{RESP3@{RESP3}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESP3}{RESP3}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_ae4a9250b0100c1a251354d64dde42300} 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+RESP3}

SDMMC response 3 register, Address offset\+: 0x1C \Hypertarget{struct_s_d_m_m_c___type_def_aebd8ffdd133537059f29fd5fecd6e290}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!RESP4@{RESP4}}
\index{RESP4@{RESP4}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESP4}{RESP4}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_aebd8ffdd133537059f29fd5fecd6e290} 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+RESP4}

SDMMC response 4 register, Address offset\+: 0x20 \Hypertarget{struct_s_d_m_m_c___type_def_a33c78086429a7eed4d57a5633a9d78f2}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!RESPCMD@{RESPCMD}}
\index{RESPCMD@{RESPCMD}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESPCMD}{RESPCMD}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a33c78086429a7eed4d57a5633a9d78f2} 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+RESPCMD}

SDMMC command response register, Address offset\+: 0x10 \Hypertarget{struct_s_d_m_m_c___type_def_a9bbd3a78b1a7fb30c53e1d17a31b9b32}\index{SDMMC\_TypeDef@{SDMMC\_TypeDef}!STA@{STA}}
\index{STA@{STA}!SDMMC\_TypeDef@{SDMMC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{STA}{STA}}
{\footnotesize\ttfamily \label{struct_s_d_m_m_c___type_def_a9bbd3a78b1a7fb30c53e1d17a31b9b32} 
\mbox{\hyperlink{core__armv81mml_8h_af63697ed9952cc71e1225efe205f6cd3}{\+\_\+\+\_\+I}} uint32\+\_\+t SDMMC\+\_\+\+Type\+Def\+::\+STA}

SDMMC status register, Address offset\+: 0x34 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
